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october 2007 rev 7 1/52 52 PM6685 dual step-down main supply controller with auxilary voltages for notebook system power features 6v to 28v input voltage range fixed 5v - 3.3v output voltages 5v and 3.3v voltage always available to deliver 100ma of peak current 1.237v 1% reference voltage available lossless current s ensing using low side mosfets' r ds(on) negative current limit soft-start internally fixed at 2ms soft output discharge latched ovp and uvp selectable pulse skipping at light loads selectable minimum frequency (33khz) in pulse skip mode 4mw maximum quiescent power independent power good signals output voltage ripple compensation applications notebook computers tablet pc or slates mobile system power supply 3 and -4 cells li+ battery-powered devices description PM6685 is a dual step-down controller specifically designed to provide extremely high efficiency conversion with loss-less current sensing technique. the constant on-time architecture assures fast load trans ient response and the embedded voltage feed-forward provides nearly constant switching frequency operation. an embedded integrator control loop compensates the dc voltage error due to the output ripple. the pulse skipping technique increases efficiency for very light loads. moreover, a minimum switching frequency of 33khz is selectable in order to avoid audio noise issues. the PM6685 provides a selectable switching frequency, allowing either 200khz/300khz, 300khz/400khz, or 400khz /500khz operation of the 5v/3.3v switching sections. vfqfpn-32 (5mm x 5mm) table 1. device summary order code package packaging PM6685 vfqfpn-32 (5mm x 5mm) tube PM6685tr vfqfpn-32 (5mm x 5mm) tape and reel www.st.com
contents PM6685 2/52 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 typical operating char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 constant on time pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 no-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7 soft start and soft end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.8 gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.9 reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.10 internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.11 power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 30
PM6685 contents 3/52 8 monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1 power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.3 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.4 undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5 design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.7 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.8 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.9 input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10 power mosfets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.11 closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 power mosfets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.4 current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.5 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6 synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.7 integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.8 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
block diagram PM6685 4/52 1 block diagram figure 1. functional block diagram ldo5 enable 5 v linear regulator reference generator 5v smps controller frequency selector level shifter startup controller ldo3 mode selector termic controller + - + - + - 4 v uvlo v ref 2.55 v 3.3 v linear regulator pgood ldo5 4.8 v uvlo v 5sw ldo3 out3 skip 3.3v smps controller fsel hgate3 boot3 phase3 level shifter hgate5 boot5 phase5 out5 csense3 comp3 lgate3 ldo5 pgood3 csense5 comp5 lgate5 ldo5 pgood5 shdn ldo3 sel en3 uvlo ldo3 enable ldo5 enable en5 termic fault v ref ldo3 enable v in + - 2.6 v v cc v cc
PM6685 pin settings 5/52 2 pin settings 2.1 connections figure 2. pin connection (top view) 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 PM6685 PM6685 skip boot5 hgate5 phase5 csense5 vin ldo5 v5sw sgnd1 shdn en3 fsel comp3 pgood_ldo3 out3 ldo3 sgnd2 boot3 hgate3 phase3 lgate3 pgnd lgate5 csense3 vref vcc comp5 out5 ldo3_sel pgood3 pgood5 en5
pin settings PM6685 6/52 2.2 functions table 2. pin functions pin name description 1 sgnd1 signal ground. reference for internal logic circuitry. it must be connected to the signal ground plan of the power supply. the signal ground plan and the power ground plan must be connected togethe r in one point near the pgnd pin. 2 comp3 dc voltage error compensation pi n for the 3.3v switching section. 3 fsel frequency selection pin. it provides a selectable switching frequency, allowing , allowing three different values of switching frequencies for the 5v/3.3v switching sections. 4en3 3.3v smps enable input. ? the 3.3v section is enabled applying a voltage greater than 2.4v to this pin. ? the 3.3v section is disabled applying a voltage lower than 0.8v. when the section is disabled the high side gate driver goes low and low side gate driver goes high. if both en3 and en5 pins are low and shdn pin is high the device enters in standby mode. 5 shdn shutdown control input. ? the device switch off if the shdn voltage is lower than 0.8v (shutdown mode) ? the device switch on if the s hdn voltage is greater than 1.7v. the shdn pin can be connected to the battery through a voltage divider to program an undervoltage lockout. in shutdown mode, the gate drivers of the two switching sections are in high impedance (high-z). 6 pgood ldo3 power good signal for the 3.3v linear regul ator. this pin is an open drain output. it is shorted to gnd if ldo3_sel pin is at its low level or if the output voltage on ldo3 pin is lower than 2.6v. 7 ldo3 3.3v linear regulator output. ldo3 can provide 100ma peak current. 8out3 output voltage sense for the 3.3v switch ing section.this pin must be directly connected to the output voltage of the switching section. 9boot3 bootstrap capacitor connection for the s witching 3.3v section. it supplies the high-side gate driver. 10 hgate3 high-side gate driver output for the 3.3v section. 11 phase3 switch node connection and return path for the high side driver for the 3.3v section. 12 csense3 current sense input for the 3.3v section. this pin must be connected through a resistor to the drain of the synchronous rectifier (r dson sensing) to set the current limit threshold. 13 lgate3 low-side gate driver output for the 3.3v section. 14 pgnd power ground. this pin must be connected to the power ground plan of the power supply. 15 lgate5 low-side gate driver output for the 5v section. 16 sgnd2 signal ground for analog circuitry. it must be connected to the signal ground plan of the power supply.
PM6685 pin settings 7/52 pin name description 17 v5sw internal 5v regulator bypass connection. ? if v5sw is connected to out5 (or to an external 5v supply) and v5sw is greater than 4.9v, the ldo5 regulator shuts down and the ldo5 pin is directly connected to out5 through a 3w (max) switch. ? if v5sw is connected to gnd, the ldo5 linear regulator is always on. 18 ldo5 5v internal regulator output. it can provide up to 100ma peak current. ldo5 pin supplies embedded low side gate drivers and an external load. 19 vin device input supply voltage. a bypass filter (4w and 4.7mf) between the battery and this pin is recommended. 20 csense5 current sense input for the 5v section. this pin must be connected through a resistor to the drain of the synchronous rectifier (r dson sensing) to set the current limit threshold. 21 phase5 switch node connection and return path for the high side driver for the 5v section. 22 hgate5 high-side gate driver output for the 5v section. 23 boot5 bootstrap capacitor connection for the 5v section. it supplies the high-side gate driver. 24 skip pulse skip mode control input. ? if the pin is connected to ldo5 the pwm mode is enabled. ? if the pin is connected to gnd, the pulse skip mode is enabled. ? if the pin is connected to vref the pulse skip mode is enabled but the switching frequency is kept higher th an 33khz (no-audible pulse skip mode). 25 en5 5v smps enable input. ? the 5v section is enabled applying a voltage greater than 2.4v to this pin. ? the 5v section is disabled applying a voltage lower than 0.8v. when the section is disabled the high side gate driver goes low and low side gate driver goes high. 26 pgood5 power good signal for the 5v section. this pin is an open drain output. the pin is pulled low if the output is disabl ed or if it is out of approximately +/- 10% of its nominal value. 27 pgood3 power good signal for the 3.3v section. this pin is an open drain output. the pin is pulled low if the output is disabl ed or if it is out of approximately +/- 10% of its nominal value. 28 ldo3sel control pin for the 3.3v internal linear regulator. this pin determines three operative modes for the ldo3. ? if ldo3_sel pin is connected to gnd the ldo3 output is always disabled. ? if ldo3_sel pin is connected to ldo5 the ldo3 internal regulator is always enabled. ? if ldo3_sel pin is connected to vref and out3 is greater than about 3v, the ldo3 regulator shuts down and the ldo3 pin is be directly connected to out3 through a 3w (max) switch. 29 out5 output voltage sense for the 5v switchi ng section.this pin must be directly connected to the output voltage of the switching section. 30 comp5 dc voltage error compensation pin for the 5v switching section.. 31 vcc device supply voltage pin. it supplies the all the internal analog circuitry except the gate drivers (see ldo5). connect this pin to ldo5. table 2. pin functions (continued)
pin settings PM6685 8/52 pin name description 32 vref high accuracy output voltage reference (1 .237v). it can deliver 50ua. bypass to sgnd with a 100nf capacitor. 33 exp pad exposed pad. table 2. pin functions (continued)
PM6685 electrical data 9/52 3 electrical data 3.1 maximum rating 3.2 thermal data table 3. absolute maximum ratings parameter value unit compx,fsel,ldo3_sel,vr ef,skip to sgnd1,sgnd2 -0.3 to vcc + 0.3 v enx,shdn,pgood_ldo3,outx,pgoodx,vcc to sgnd1,sgnd2 -0.3 to 6 v ldo3 to sgnd1,sgnd2 -0.3 to ldo5 + 0.3 v lgatex to pgnd -0.3 (1) to ldo5 + 0.3 1. lgatex to pgnd up to -1v for t < 40ns v hgatex and bootx, to phasex -0.3 to 6 v phasex to pgnd -0.6 (2) to 36 2. phase to pgnd up to -2.5v for t < 10ns v csensex , to pgnd -0.6 to 42 v csensex to bootx_ -6 to 0.3 v v5sw, ldo5 _to pgnd -0.3 to 6 v vin to pgnd -0.3 to 36 v pgnd to sgnd1,sgnd2_ -0.3 to 0.3 v power dissipation at tamb = 25oc 2 w maximum withstanding voltage range test condition: cdf-aec-q100-002- ?human body model? acceptance criteria: ?normal performance? vin pin 1000 v other pins 2000 table 4. thermal data symbol parameter value unit r thja thermal resistance junction to ambient 35 c/w t stg storage temperature range -40 to 150 c t j junction operating temperature range -10 to 125 c
electrical characteristics PM6685 10/52 4 electrical characteristics v in = 12v, t a = 0c to 85c, unless otherwise specified table 5. electrical characteristics symbol parameter test condition min typ max unit supply section vin input voltage range vout=vref, ldo5 in regulation fsel to gnd 5.5 28 v vcc ic supply voltage 4.5 5.5 v v v5sw turn-on voltage threshold 4.8 4.9 v turn-off voltage threshold 4.6 4.75 v hysteresis 20 50 mv v v5sw maximum operating range 5.5 v rdson ldo5 internal bootstrap switch resistance v5sw > 4.9v 1.8 3 ? rdson ldo3 internal bootstrap switch resistance vout3 = 3.3v 1.8 3 ? out3, out5 discharge mode on-resistance 16 25 ? out3, out5_ discharge mode synchronous rect ifier turn-on level 0.2 0.35 0.5 v pin operating power consumption v out5 >5.1v,v out3 >3.34v v5sw to 5v ldo5, ldo3 no load 4mw ish v in shutdown current shdn connected to gnd, 14 18 a isb v in standby current enx to gnd, v5sw to gnd, ldo3_sel to 5v 270 380 a shutdown section v shdn device on threshold 1.2 1.5 1.7 v device off threshold 0.8 0.85 0.9 v soft start section soft start ramp time 2 3.5 ms
PM6685 electrical characteristics 11/52 symbol parameter test condition min typ max unit current limit and zero crossing comparator i csense input bias current limit 90 100 110 a comparator offset v csense -v pgnd -6 6 mv zero crossing comparator offset v pgnd -v phase -1 11 mv fixed negative current limit threshold v pgnd -v phase -120 mv on time pulse width ton on-time duration fsel to gnd out5=5v 1685 1985 2285 ns out3=3.3v 780 920 1060 fsel to vref out5=5v 1115 1315 1515 out3=3.3v 585 690 795 fsel to ldo5 out5=5v 830 980 1130 out3=3.3v 470 555 640 off time t offmin minimum off time 400 500 ns voltag e reference v ref voltage accuracy 4.2v uvlo, i ldo3 =0a v out5 >5.1v, v out3 >3.34v 270 350 400 ma uvlo under voltage lockout of ldo5 3.94 4 4.13 v table 5. electrical characteristics (continued)
electrical characteristics PM6685 12/52 symbol parameter test condition min typ max unit ldo3 linear regulator v ldo3 ldo3 linear output voltage 0.5ma uvlo 130 165 200 ma high and low gate drivers hgate driver on-resistance hgatex high state (pullup) 2.0 3 ? hgatex low state (pulldown) 1.6 2.7 ? lgate driver on-resistance lgatex high state(pullup) 1.4 2.1 ? lgatex low state (pulldown) 0.8 1.2 ? pgood pins uvp/ ovp protections ovp over voltage threshold both smps sections with respect to vref. 113 116 120 % uvp under voltage threshold 66 70 72 % pgood3,5 upper threshold (vfb-vref) 107 110 113 % lower threshold (vfb-vref) 90 92 94 % i pgood3,5 pgood leakage current v pgood3,5 forced to 5.5v 1 ua v pgood3,5 output low voltage isink = 4ma 150 250 mv pgood ldo3 rising voltage threshold 77.7 81.1 % falling voltage threshold 72.1 76.6 % hysteresis 20 30 mv i pgood_ldo3 pgood leakage current v pgood ldo3 forced to 5.5v 1 ua v pgood_ldo3 output low voltage isink = 4ma 150 250 mv thermal shutdown t sdn shutdown temperature 150 c power management pins en3,5 smps disabled threshold (2) 0.8 v smps enabled threshold (2) 2.4 fsel frequency selection range low level (2) 0.5 v middle level (2) 1.0 v ldo5 -1.5 high level (2) v ldo5 -0.8 table 5. electrical characteristics (continued)
PM6685 electrical characteristics 13/52 symbol parameter test condition min typ max unit ldo3 sel 3.3v linear regulator selection pin always-off level (2) 0.5 bootstrap level (2) 1.0 v ldo5 -1.5 always-on level (2) v ldo5 -0.8 skip pulse skip mode (2) 0.5 v pwm mode (2) 1.0 v ldo5 -1.5 frequency clamp mode (2) v ldo5 -0.8 input leakage current v en3,4 = 0 to 5v 1 a v skip = 0 to 5v 1 v shdn = 0 to 5v 0.1 v fsel = 0 to 5v 1 v ldo3_sel = 0 to 5v 1 1. by demoboard test 2. by design table 5. electrical characteristics (continued)
typical operating characteristics PM6685 14/52 5 typical operating characteristics fsel = gnd (200/300khz), skip = gn d (skip mode), ldo3_sel = vref, v5sw = out5, input voltage vin = 12v, shdn, en3 and en5 high, no load unless specified. figure 3. 5v output efficiency vs load current figure 4. 3.3v output efficiency vs load current figure 5. pwm no load input battery vs input voltage figure 6. skip no load battery current vs input voltage
PM6685 typical operating characteristics 15/52 figure 7. standby mode input battery current vs input voltage figure 8. shutdown mode input device current vs input voltage figure 9. 5v switching frequency vs load current figure 10. 3.3v switching frequency vs load current figure 11. ldo5 vs output voltage figure 12. ldo3 vs output voltage
typical operating characteristics PM6685 16/52 figure 13. 5v voltage regulation vs load current figure 14. 3.3v voltage regulation vs load current figure 15. voltage reference vs load current figure 16. out5, ldo3 and ldo5 power-up figure 17. 5v pwm load transient figure 18. 3.3v pwm load transient
PM6685 typical operating characteristics 17/52 figure 19. 5v soft start (0.75 ? load) figure 20. 3.3v soft start (0.55 ? load) figure 21. 5v soft end (no load) figure 22. 3.3v soft end (no load) figure 23. 5v soft end (1 ? load) figure 24. 3.3v soft end (1 ? load)
typical operating characteristics PM6685 18/52 figure 25. 5v no audible skip mode figure 26. 3.3v no audible skip mode
PM6685 application schematic 19/52 6 application schematic figure 27. simplified application schematic sgnd sgnd + sgnd sgnd 3.3v+ 1 pgnd boot2 sgnd v+ + pgoodldo3 pgnd sgnd pgnd + pgood3 v+ pgnd vin + sgnd PM6685 sgnd boot1 v+ sgnd 3.3v- 1 23 22 21 20 17 29 30 25 16 15 26 27 5 4 32 24 3 31 18 19 9 10 11 12 14 1 8 2 6 28 7 13 boot5 hgate5 phase5 csense5 v5sw out5 comp5 en5 sgnd2 lgate5 pgood5 pgood3 shdn en3 vref skip fsel vcc ldo5 vin boot3 hgate3 phase3 csense3 pgnd sgnd out3 comp3 pgood ldo3 ldo3sel ldo3 lgate3 v+ sgnd pgood5 v+ 5v- 1 sgnd v+ vin pgnd 5v+ 1
device description PM6685 20/52 7 device description the PM6685 is a dual step-down controller dedicated to provide logic voltages for notebook computers. it is based on a constant on time control architec ture. this type of control offers a very fast load transient response with a minimum external component count. a typical application circuit is shown in figure 27 on page 19 . the PM6685 regulates two fixed output voltages: 5v and 3.3v. the switching frequency of the two sections can be adjusted to approximately 200/300khz, 300/400khz or 400/5 00khz respectively. in order to maximize the efficiency at light load condition, a pulse skipping mode can be selected. the PM6685 includes also two linear regulators (ldo5 and ldo3) that allow the shutdown of the respective switching sections in low consumption status. on the other hand, to maximize the efficiency in higher consumption status, the linear regulators can be turned off and their outputs can be supplied directly from the switching outputs. the PM6685 provides protection versus overvoltage, undervoltage and overtemperature as well as power good signals for monitoring purposes. an external 1.237v reference is available. 7.1 constant on time pwm control if the skip pin is tied to 5v, the device works in pwm mode. each power section has an independent on time control.the PM6685 implements a pseudo-fixed switching frequency, constant on time (cot) controller as core of the switched mode section. each power section has an independent cot control. the cot controller is based on a relatively simple algorithm and uses the ripple voltage due to the output capacitor?s esr to trigger the fixed on-time one-shot generator. in this way, the output capacitor?s esr acts as a current sense resistor providing the appropriate ramp signal to the pwm comparator. on-time one-shot duration is directly proportional to the output voltage vout, sensed at the out5/out3 pins, and inversely proportional to the input voltage vin, sensed at the vin pin, as follows: equation 1 this leads to a nearly constant switching frequency, regardless of input and output voltages. when the output voltage goes lower than the regulated voltage vreg, the on-time one shot generator directly drives the high side mosfet for a fixed on time allowing the inductor current to increase; after the on time, an off time phase, in which the low side mosfet is turned on, follows. figure 28 on page 21 shows the inductor current and the output voltage waveforms in pwm mode. in out on v v k t =
PM6685 device description 21/52 figure 28. constant on time pwm control the duty cycle d of the buck converter in steady state is: equation 2 the pwm control works at a nearly fixed frequency f sw : equation 3 as mentioned the steady state switching frequency is theoretically independent from battery voltage and from output voltage. actually th e frequency depends on pa rasitic voltage drops that are present during the charging path (hig h side switch resistan ce, inductor resistance (dcr)) and discharging pa th (low side switch resistance, dcr). as a result the switching frequency increases as a function of the load current. standard switching frequency values can be selected for both sections by pi n fsel as shown in the following table: t o n t o ff inductor current t output voltage vreg dc error in out v v d = on in out on in out on sw k 1 v v k v v t d f = = =
device description PM6685 22/52 the values in the table are measured with v in =12v, operation mode = pwm and i load = 2a. the other output are unloaded. 7.2 constant on time architecture figure 29 on page 23 shows the simplified block diagram of a constant on time controller. a minimum off-time constrain (380ns typ) is introduced to allow inductor valley current sensing on the synchronous switch. a minimum on-time(150ns typ) is also introduced to assure the start-up switching sequence. PM6685 has a one-shot generator for each power section that turns on the high side mosfet when the following conditions are satisfied simultaneously: the pwm comparator is high, the synchronous rectif ier current is below the current limit threshold, and the minimum off-time has timed out. once the on-time has timed out, the high side switch is turned off, while the synchronous switch is turn ed on according to the anti-cross conduction circuitry management. when the negative input voltage at the pwm comparator, which is a scaled-down replica of the output voltage ripple (see the r fb1 /r fb2 divider in figure 29 ), reaches the valley limit (determined by internal reference v r =0.9v), the low-si de mosfet is turned off according to the anti-cross conduction logic once again, and a new cycle begins. table 6. fsel pin selection fsel smps 5v smps 3.3v frequency k on frequency k on sgnd 212khz 4,7us 297,6khz 3.36us vref 323khz 3us 400khz 2.5us ldo5 432khz 2.31us 500khz 2.0us
PM6685 device description 23/52 figure 29. constant on-time block diagram 7.3 output ripple compensation in a classic constant on time control, the system regulates the valley value of the output voltage and not the average value, as shown in figure 28 on page 21 . in this co ndition, the output voltage ripple is sour ce of a dc static error. to compensate this error, an integrator network can be introduced in the control loop, by connecting the output voltage to the co mp5/comp3(for the 5v and 3.3v sections respectively) pin through a capacitor c int as in figure 30 on page 24 . + - hs hs driver driver level level shifter shifter ls ls driver driver q q r s ldo5 ldo5 q r s pwm pwm comparator comparator positive positive current limit current limit vr vr + - zero zero - - cross. cross. comp. comp. bandgap bandgap 1.236v 1.236v skip skip vref vref phase phase pgnd pgnd lgate lgate hgate hgate boot boot csense csense - comp comp gm gm out out rfb1 rfb1 rfb2 rfb2 vr vr vr vr + + - toff toff - - min min ton ton + - vin vin 0.5v + - 0.5v + - 0.25v ldo5 ldo5 + - hs hs driver driver level level shifter shifter ls ls driver driver q q r s ldo5 ldo5 q r s pwm pwm comparator comparator positive positive current limit current limit vr vr + - zero zero - - cross. cross. comp. comp. bandgap bandgap 1.236v 1.236v skip skip vref vref phase phase pgnd pgnd lgate lgate hgate hgate boot boot csense csense - comp comp gm gm out out rfb1 rfb1 rfb2 rfb2 vr vr vr vr + + - + - toff toff - - min min ton ton + - vin vin 0.5v + - 0.5v + - 0.5v + - 0.25v + - 0.25v ldo5 ldo5
device description PM6685 24/52 figure 30. circuitry for output ripple compensation the integrator amplifier generates a current, proportional to the dc errors, which decreases the output voltage in order to compensate the total static error, including the voltage drop on pcb traces. in addition, c int provides an ac path for the output ripple. in steady state, the voltage on comp5/comp3 pin is the sum of the reference voltage v r and the output ripple (see figure 30 ). in fact when the voltage on the comp pin reaches v r , a fixed ton begins and the output increases. for example, we consider v out =5v with an output ripple of ? v=50mv. considering c int >>c filt , the c int dc voltage drop v cint is about 5v-vr+25mv=4.125v. c int ensures an ac path for the output voltage ripple. then th e comp pin ripple is a replica of the output ripple, with a dc value of vr+25mv=925mv. for more details about the output ripple compensation network, see the paragraph ? closing the integrator loop ? in the design guidelines . 7.4 pulse skip mode if the skip pin is tied to ground, the device works in skip mode. at light loads a zero-crossing comparator tr uncates the low-side switch on-time when the inductor current becomes negative. in this co ndition the section works in discontinuous conduction mode. the threshold between continuous and discontinuous conduction mode is: equation 4 + - vr vr - comp comp gm gm out out rfb1 rfb1 rfb2 rfb2 vr vr + pwm pwm comparator comparator cint cint rint rint cfilt cfilt t vr cout cout comp pin voltage l l d d output voltage i=gm(v1-vr) v1 v1 t ? v ? v vcint vcint rout rout + - vr vr - - comp comp gm gm out out rfb1 rfb1 rfb2 rfb2 vr vr + pwm pwm comparator comparator cint cint rint rint cfilt cfilt t vr cout cout comp pin voltage l l d d output voltage i=gm(v1-vr) v1 v1 t ? v ? v vcint vcint rout rout on out in t l 2 v v ) skip ( iload ? =
PM6685 device description 25/52 for higher loads the inductor current doesn?t cross the zero and the device works in the same way as in pwm mode and the frequency is fixed to the nominal value. figure 31. pwm and pulse skip mode inductor current figure 31 shows inductor current waveforms in pwm and skip mode. in order to keep average inductor current equal to load current, in skip mode some switching cycles are skipped. when the output ripple reaches the regulated voltage vreg, a new cycle begins. the off cycle duration and the switching frequency depend on the load condition. as a result of the control technique, losses are reduced at light load s, improving the system efficiency. 7.5 no-audible skip mode if skip pin is tied to v ref , a no-audible skip mode with a minimum switching frequency of 33khz is enabled. at light load condition, if there is not a new switching cycle within a 30us(typ.) period, a no-audible skip mode cycle begins. figure 32. frequency clamp skip mode the low side switch is turned on until the output voltage crosses about vreg+1%. then the high side mosfet is turned on for a fixed on time period. afterwards the low side switch is enabled until the inductor current reaches the zero-crossing threshold. this keeps the switching frequency higher than 33khz. as a consequence of the control, the regulated voltage can be slightly higher than vreg (up to 1%). time ton1 toff 0 inductor current pwm mode pulse skip mode ton2 low side off toff low side on load current ton1=ton2 time 0 inductor current no-audible skip mode low side
device description PM6685 26/52 if, due to the load, the frequency is higher than 33khz, the device works like in skip mode. no-audible skip mode reduces audio frequency noise that may occur in pulse skip mode at very light loads, keeping the efficiency higher than in pwm mode. 7.6 current limit the current-limit circuit employs a ?valley? cu rrent-sensing algorithm. during the conduction time of the low side mosfet the current flowing through it is sensed. the current-sensing element is the low side mosfet on-resistance( figure 33 ) figure 33. r dson sensing technique an internal 100 a ? i l current source (i csense ) is connected to c sense pin and determines a voltage drop on r csense . if the voltage across the sensin g element is greater than this voltage drop, the controller doesn?t initiate a new cycle. a new cycle starts only when the sensed current goes below the current limit. since the current limit circuit is a valley current limit, the actual peak current limit is greater than the current limit threshold by an amount equal to the inductor ripple current. moreover the maximum output current is equal to the valley cu rrent limit plus half of the inductor ripple current: equation 5 the output current limit depends on the current ripple, as shown in figure 34 on page 27 : lgate hgate csense phase rcsense rds on hs ls 2 i i (max) i l lvalley load ? + =
PM6685 device description 27/52 figure 34. current waveforms in current limit conditions being fixed the valley threshold, the greater the current ripple is, greater the dc output current is the valley current limit can be set with resistor r csense : equation 6 where i csense = 100ua, r dson is the drain-source on resistance of the low side switch. consider the temperature effect and the worst case value in r dson calculation. the accuracy of the valley current threshold detection depends on the offset of the internal comparator ( ? v off ) and on the accuracy of the current generator( ? i csense ): equation 7 where rsns is the sensing element (r dson ). PM6685 provides also a fixed negative peak current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in pwm mode. this negative current limit threshold is measured between phase and sgnd pins, comparing the magnitude drop on the phase node during the conduc tion time of the low side mosfet with an internal fixed voltage of 120mv. if the current is sensed on the low side mosf et, the negative valley- current limit ineg (if the device works in pwm mode) is given by: inductor current valley current threshold dc current limit = maximum load current time maximum load current is influenced by the inductor current ripple csense lvalley dson csense i i r r = sns sns csense csense csense csense off csense csense lvalley lvalley r r r r 100 i r v i i i i ? + ? + ? ? ? ? ? ? ? + ? = ?
device description PM6685 28/52 equation 8 7.7 soft start and soft end each switching section is enabled separately by asserting high en5/en3 pins respectively. in order to realize the soft start, at the start up the overcurrent threshold is set 25% of the nominal value and the undervoltage protection (see related sections) is disabled. the controller starts charging the output capacitor working in current limit. the overcurrent threshold is increased from 25% to 100% of the nominal value with steps of 25% every 700 s (typ.). after 2.8ms (typ.) the undervoltage protection is enabled. the soft start time is not programmable. a minimum capacitor c int is required to ensure a soft start without any overshoot on the output: equation 9 figure 35. soft start waveforms when a switching section is turned off(en5/en3 pins low), the controller enters in soft end mode. the output capacitor is discharged through an internal 16 ? p-mosfet switch; when the output voltage reaches 0.3v, the low-side mosfet turns on, keeping the output to ground. the soft end time also depends on load condition. dson neg r mv 120 i = out l lvalley int c 2 i 4 i ua 6 c ? + en5/en3 current limit threshold switching output time
PM6685 device description 29/52 7.8 gate drivers the integrated high-current drivers allow to use different power mosfets. the high side driver mosfet uses a bootstrap circuit whic h is indirectly supplied by ldo5 output. the boot and phase pins work respectively as s upply and return rails for the hs driver. the low side driver uses the internal ldo5 output for the supply rail and pgnd pin as return rail. an important feature of the gate drivers is the adaptive anti-cross conduction protection, which prevents high side and low side mosfets from being on at the same time. when the high side mosfet is turned off the voltage at the phase node begins to fall. the low side mosfet is turned on when the voltage at the phase node reaches an internal threshold. when the low side mosfet is turned off, the high side remains off until the lgate pin voltage goes approximately under 1v. the power dissipation of the drivers is a function of the total gate charge qg of the external power mosfets and of the switching frequency, as shown in the following equation: where vdriver is the 5v driver supply. 7.9 reference voltage and bandgap the 1.237v(typ.) internal bandgap voltage is accurate to 1% over the temperature range. it is externally available (vref pin) and can supply up to 100 a and can be used as a voltage threshold for the multifunction pins fsel, skip and ldo3_ sel to select the appropriate working mode. bypass vref to ground with a 100nf minimum capacitor. if vref goes below 0.87v(typ.) , the system detects a fault condition and all the circuitry is turned off. a toggle on the input voltage (power on reset) or a toggle on shdn pin is necessary to restart the device. an internal divider of the bandgap provides a voltage reference vr of 0.9v. this voltage is used as reference for the linear and the swit ching regulators outputs. the overvoltage protection, the undervoltage protection and the power good signals are referred to vr. 7.10 internal lin ear regulators the PM6685 has two linear regulators providing respectively 5v(ldo5) and 3.3v(ldo3) at 2% accuracy. high side drivers, low side drivers and most of internal circuitry are supplied by ldo5 output through vcc pin (an external rc filter may be applied between ldo5 and vcc). both linear regulators can provide an average output current of 50ma and a peak output current of 100ma. bypass both ldo5 and ldo3 outputs with a minimum 1 f ceramic capacitor and a 4,7 f tantalum capacitor (esr < 2 ? ). if the 5v output goes below 4v, the system detects a fault condition and all th e circuitry is turned off. a power on reset or a toggle on shdn pin is necessary to restart the device. sw g driver driver f q v p =
device description PM6685 30/52 v5sw pin allows to keep the 5v linear regulator always active or to enable the internal bootstrap-switch over function: if the 5v sw itching output is connected to v5sw, when the voltage on v5sw pin is above 4.8v, an internal 3.0 ? max p-channel mosfet switch connects v5sw pin to ldo5 pin and simultane ously ldo5 shuts down. this configuration allows to achieve higher efficiency. v5sw can be connected also to an external 5v supply. ldo5 regulator turns off and ldo5 is supplied externally. if v5sw is connected to ground, the internal 5v regulator is always on and supplies ldo5 output. the 3.3v linear regulator is supplied by ldo5 output. ldo3_sel pin allows to keep 3.3v linear regulator always enabled, always disabled or to enable the internal bootstrap-switch over function. according to ta b l e 7 : if ldo3_sel is connected to vref pin, when the power good signal of the 3.3v switching output voltage pgood3(see relate d sections) is high, the internal linear regulator is turned off and ld o3 output is connected direct ly to out3 pin through an internal 3 ? max p-channel mosfet switch. if ldo3_sel is connected to 5v, the internal 3.3v regulator is always on and supplies ldo3 output. if ldo3_sel is connected to ground, the internal 3.3v regulator is always off and ldo3 output is clamped to ground. 7.11 power up sequencin g and operative modes let?s consider shdn, en5 and en3 low at the beginning. the battery voltage is applied as input voltage. the device is in shutdown mode. when the shdn pin voltage is above the shut down device on threshold(1.5v typ.), the controller begins the power-up sequence. all the latched faults are cleared. ldo5 undervoltage control is blanked for 4 ms and the internal regulator ldo5 turns on. if the ldo5 output is above the uvlo threshold after this time, the device enters in standby mode. the switching outputs are kept to ground by turning on the low side mosfets. table 7. v5sw multifunction pin v5sw description gnd the 5v linear regulator is always turned on and supplies ldo5 output. switching 5v output the 5v linear regulator is turned off w hen the voltage on v5sw is above 4.8v and ldo5 output is supplied by the switching 5v output. external 5v supply the 5v linear regulator is turned off w hen the voltage on v5sw is above 4.8v and ldo5 output is supplied by the external 5v. table 8. ldo3_sel multifunction pin ldo3_sel description gnd the 3.3v linear regulator is always turned off. vref the 3.3v linear regulator is turned off when pgood3 is high. ldo3 output is supplied by the switching 3.3v output. ldo5 the 3.3v linear regulator is always turned on and supplies ldo3 output.
PM6685 device description 31/52 when en5 and en3 pins are forced high the switching sections begin their soft start sequence. ldo3 management is independent from the general power up sequence and depends only on ldo3_sel . table 9. operatives modes mode conditions description run shdn is high en3/en5 pins are high switching regulators are enabled; internal linear regulators outputs are enabled. stand by both en5/en3 pins are low and shdn pin is high internal linear regulators active (ldo5 is always on while ldo3 depends on ldo3_sel pin). in standby mode lgate5/lgate3 pins are forced high while hgate5/hgate3 pins are forced low. shutdown shdn is low all circuits off.
monitoring and protections PM6685 32/52 8 monitoring and protections 8.1 power good signals the PM6685 provides three independent power good signals: one for each switching section(pgood5/pgood3) and the other for the internal linear regulator ldo3(pgood_ldo3). pgood5/pgood3 signals are low if the output vo ltage is out of 10% of the designed set point or during the soft-start, the soft end and when the device works in standby and shutdown mode. pgood_ldo3 signal is low when the output voltag e of ldo3 output is lower than its falling voltage threshold(2.6v typ.). each power go od pin is an open-drain output and can sink current up to 4ma. 8.2 thermal protection the PM6685 has a thermal protection to preserve the device from overheating. the thermal shutdown occurs when the die temperature goes above +150c. in this case all internal circuitry is turned off and the power sections are turned off after the discharge mode. a power on reset or a toggle on the shdn pin is necessary to restart the device. 8.3 overvoltage protection when the switching output voltage is about 115% of its nominal value, a latched overvoltage protection occurs. in this case, the synchronous rectifier immediately turns on while the high-side mosfet turns off. the output capacitor is rapidly discharged and the load is preserved from being damaged. the over voltge protection is also active during the soft start. once an overvoltage protection ha s been detected, a toggle on shdn, en3/en5 pins or a power on reset is necessa ry to exit from the latched state. 8.4 undervoltage protection when the switching output voltage is below 70% of its nominal value, a latched undervoltage protection occurs. in this case the switching section is immediately disabled and both switches are open. the controller enters in soft end mode and the output is eventually kept to ground, turning low side mosfet on. the undervoltage circuit protection is enabled only at the end of the soft-start. once an overvoltage protection has been detected, a toggle on shdn, en5/en3 pin or a power on reset is necessary to clear the undervoltage fault and starts with a new soft-start phase.
PM6685 monitoring and protections 33/52 8.5 design guidelines the design of a switching section starts from two parameters: input voltage range: in notebook applications it varies from the minimum battery voltage, vinmin to the ac adapter voltage, vinmax. maximum load current: it is the maximu m required output current, iload(max). 8.6 switching frequency it?s possible to set 3 different working frequency ranges for the two sections: 200khz/300khz, 400khz/500khz, 600khz/700khz with fsel pin. switching frequency mainly influences two parameters: inductor size: for a given saturation current and rms current, greater frequency allows to use lower inductor values, which means smaller size. efficiency: switching losses are proportiona l to frequency. high frequency generally involves low efficiency. 8.7 inductor selection once that switching frequency is defined, inductor selection depends on the desired inductor ripple current and load transient performance. low inductance means great ripple current and could generate great output noise. on the other hand, low inductor values involve fast load transient response. a good compromise between the transient response time, the efficiency, the cost and the size is to choose the inductor value in order to maintain the inductor ripple current ? il between 20% and 50% of the maximum output current iload(max). the maximum ? il occurs at the maximum input voltage. with this considerations, the inductor value can be calculated with the following relationship: table 10. protections and operatives modes mode conditions description overvoltage protection out5/out3 > 115% of the nominal value lgate 5/lgate3 pin is forced high, ldo5 remains active. exit by a power on reset or toggling shdn or en5/en3 undervoltage protection out5/out3 < 70% of the nominal value lgate5/lgate3 is forced high after the soft end mode, ldo5 remains active. exit by a power on reset or toggling shdn or en5/en3 thermal shutdown t j > +150 c all circuitry off. exit by a por on vin or toggling shdn.
monitoring and protections PM6685 34/52 equation 10 where fsw is the switching frequ ency, vin is the input voltage, vout is the output voltage and ? il is the selected inductor ripple current. in order to prevent overtemperature working conditions, inductor must be able to provide an rms current greater than the maximum rms inductor current ilrms: equation 11 where ? il(max) is the maximum ripple current: equation 12 if hard saturation inductors are used, the inductor saturation current should be much greater than the maximum inductor peak current ipeak: equation 13 using soft saturation inductors it?s possible to choose inductors with saturation current limit nearly to ipeak. below there is a list of some inductor manufacturers. table 11. inductor manufacturer manufacturer series inductor value (uh) rm s current (a) saturation current (a) coilcraft ser1360 4 to 8 6 to 8.6 7 to 12 coilcraft mlc 2.2 to 4.5 13.6 to 8.8 11.5 to 17 tdk rlf12560 2.7 to 10 7.5 to 11.5 7.5 to 14.4 in out l sw out in v v i f v v l ? ? = 12 (max)) i ( (max)) i ( i 2 l 2 load lrms ? + = max in out sw out max in l v v l f v v (max) i ? = ? 2 (max) i (max) i ipeak l load ? + =
PM6685 monitoring and protections 35/52 8.8 output capacitor the selection of the output capa citor is based on the esr value rout and the voltage rating rather than on the capacitor value cout. the output capacitor has to satisfy the output voltage ripple requirements. lower inductor value can reduce the size of the choke but increases the inductor current ripple ? il. since the voltage ripple vrippleout is given by: equation 14 a low esr capacitor is required to reduce the output voltage ripple. switching sections can work correctly even with 20mv output ripple. however, to reduce jitter noise between the two switching sections it?s preferable to work with an output voltage ripple greater than 30mv. if lower output ripple is required, a further compensation network is needed (see closing the integrator loop paragraph). finally the output capacitor choice deeply impacts on the load transient response (see load transient response paragraph). below there is a list of some capacitor manufacturers. 8.9 input capacitors selection in a buck topology converter the current that fl ows into the input capacitor is a pulsed current with zero average value. the input rms current of the two switching sections can be roughly estimated as follows: equation 15 where d1, d2 are the duty cycles and i1, i2 are the maximum load currents of the two sections. input capacitor should be chosen with an rms rated current higher than the maximum rms current given by both sections. table 12. output capacitor manufacturer manufacturer series capacitor value ( f) rated voltage (v) esr max (m ? ) sanyo poscap tpb,tpd 150 to 330 4 to 6.3 35 to 65 panasonic spcap ud, ue 150 to 220 4 to 6.3 9 to 18 l out rippleout i r v ? = ? + ? =
monitoring and protections PM6685 36/52 tantalum capacitors are good in term of low esr and small size, but they occasionally can burn out if subjected to very high curren t during the charge. ceramic capacitors have usually a higher rms current rating with smaller size and they remain the best choice. below there is a list of some ceramic capacitor manufacturers. 8.10 power mosfets logic-level mosfets are recommended, since low side and high side gate drivers are powered by ldo5. their breakdown voltage vbr dss must be higher than vinmax. in notebook applications, power management efficiency is a high level requirement. the power dissipation on the power switches becomes an important factor in switching selections. losses of high-side and low-side mosfets depend on their working conditions. the power dissipation of the high-side mosfet is given by: equation 16 maximum conduction losses are approximately: equation 17 where rdson is the drain-source on resistance of the high side mosfet. switching losses are approximately: equation 18 where ton and toff are the switching times of th e turn off and turn off phases of the mosfet. table 13. input capacitor manufacturer manufacturer series capacitor value ( f) rated voltage (v) tayio yuden umk325bj106km-t10 10 50 tayio yuden gmk325bj106mn 10 35 tdk c3225x5r1e106m 10 25 switching conduction dhighside p p p + = 2 load min in out dson conduction (max) i v v r p = 2 f t ) 2 i (max) i ( v 2 f t ) 2 i (max) i ( v p sw off l load in sw on l load in switching ? + + ? ? =
PM6685 monitoring and protections 37/52 as general rule, high side mosfets with low gate charge are recommended, in order to minimize driver losses. below there is a list of possible choices for the high side mosfet. the power dissipation of the low side mosfet is given by: equation 19 maximum conduction losses occur at the maximum input voltage: equation 20 choose a synchronous rectifier with low rdson. when high side mosfet turns on, the fast variation of the phase node volt age can bring up even the low side gate through its gate- drain capacitance crss, causing cross-conduction problems. choose a low side mosfet that minimizes the ratio crss/cgs (cgs = ciss - crss). below there is a list of some possible low side mosfets. dual n-channel mosfets can be used in applications with a maximum output current of about 3 a. below there is a list of some mosfet manufacturers. table 14. high side mosfet manufacturer manufacturer type gate charge (nc) rated reverse voltage (v) st sts12nh3ll 10 30 st sts17nh3ll 18 30 table 15. low side mosfet manufacturer manufacturer type rdson (m ? ) rated reverse voltage (v) st sts17nf3ll 5.5 0.047 30 st sts25nh3ll 3.5 0.011 30 conduction dlowside p p = ? ? ? ? ? ? ? ? ? = gs rss c c
monitoring and protections PM6685 38/52 a rectifier across the low side mosfet is recommended. the rectifier works as a voltage clamp across the synchronous rectifier and re duces the negative inductor swing during the dead time between turning the high-side mosfet off and the synchronous rectifier on. it can increase the efficiency of the switching se ction, since it reduces the low side switch losses. a schottky diode is suitab le for its low forward voltage drop (0.3v). the diode reverse voltage must be greater than the maximum input voltage vinmax. a minimum recovery reverse charge is preferable. below there is a list of some schottky diode manufacturers. 8.11 closing the integrator loop the design of external feedback network depends on the output voltage ripple. if the ripple is higher than approximately 30mv, the feedback network ( figure 36 ) is usually enough to keep the loop stable. figure 36. circuitry for output ripple compensation table 16. dual mosfet manufacturer manufacturer type rdson (m ? ) gate charge (nc) rated reverse voltage (v) st sts8dnh3ll 25 10 30 st sts4dnf60l 65 32 60 table 17. schottky diode manufacturer manufacturer series forward voltage (v) rated reverse voltage (v) reverse current (ua) st stps1l30m 0.34 30 0.00039 st stps1l20m 0.37 20 0.000075 + - vr vr - comp comp gm gm out out rfb1 rfb1 rfb2 rfb2 vr vr + pwm pwm comparator comparator cint cint rint rint cfilt cfilt t vr cout cout comp pin voltage l l d d output voltage i=gm(v1-vr) v1 v1 t ? v ? v vcint vcint rout rout + - vr vr - - comp comp gm gm out out rfb1 rfb1 rfb2 rfb2 vr vr + pwm pwm comparator comparator cint cint rint rint cfilt cfilt t vr cout cout comp pin voltage l l d d output voltage i=gm(v1-vr) v1 v1 t ? v ? v vcint vcint rout rout
PM6685 monitoring and protections 39/52 the stability of the system depe nds firstly on the output capa citor zero frequency. the following condition should be satisfied: equation 21 where k is a design parameter greater than 3 and rout is the esr of the output capacitor. it determinates the minimum integrator capacitor value cint: equation 22 where gm=50us is the integrator transconductance. in order to ensure stability it must be also verified that: equation 23 in order to reduce ground noise due to load transient on the other section, it is recommended to add a resistor rint and a capaci tor cfilt that, together with cint, realize a low pass filter (see figure 36 ). the cutoff frequency fcut must be much greater (10 or more times) than the switching frequency of the section: equation 24 due to the capacitive divider (cint, cfilt), the ripple voltage at the comp pin is given by: equation 25 out out zout sw r c 2 k f k f = > out zout sw m int v vr f k f 2 g c ? ? ? ? ? ? ? > out zout m int v vr f 2 g c > filt int filt int cut int c c c c f 2 1 r + = q v c c c v v rippleout filt int int rippleout ripple int = + =
monitoring and protections PM6685 40/52 where vrippleout is the output ripple and q is the attenuation factor of the output ripple. if the ripple is very small (lower than approximately 30mv), a further compensation network, named virtual esr network, is needed. this additional part generates a triangular ripple that is added to the esr output voltage ripple at the input of the integrator network. the complete control schematic is represented in figure 37 . figure 37. virtual esr network the t node voltage is the sum of the output voltage and the triangular waveform generated by the virtual esr network. in fact the virtual esr network behaves like a further equivalent esr resr. a good trade-off is to design the network in order to achieve an resr given by: equation 26 where ? il is the inductor current ripple and vripple is the overall ripple of the t node voltage. it should be chosen higher than approximately 30mv. the stability of the system d epends firstly on th e output capacitor value and on rtot: + - v v r r c c o o m m p p g g m m o o u u t t r r f f b b 1 1 r r f f b b 2 2 v v r r + p p w w m m c c o o m m p p a a r r a a t t o o r r c c i i n n t t r r i i n n t t c c f f i i l l t t t vr c c o o u u t t comp pin v oltage l l d d output voltage i=gm(v1- v r) v v 1 1 c c r r 1 1 r r t t t t node voltage ? v ? v 1 r r o o u u t t ? v 1 out l ripple esr r i v r ? ? =
PM6685 monitoring and protections 41/52 equation 27 the following condition should be satisfied: equation 28 where k is a free design parameter greater than 3 and determines the minimum integrator capacitor value cint: equation 29 in order to ensure stability it must be also verified that: equation 30 c must be selected as shown: equation 31 r must be chosen in order to have enough ripple voltage on integrator input: out esr tot r r r + = = > out z sw m int v vr f k f 2 g c ? ? ? ? ? ? ? > out zout m int v vr f 2 g c > int c 5 c >
monitoring and protections PM6685 42/52 equation 32 r1 can be selected as follows: equation 33 example: 5v section, fsw=200khz, l=4.7uh , cout=100uf ceramic (rout~0 ? ). we design resr = 30m ? . we choose cint=1nf by equations 31, 32 and cfilt=47pf, rint=1.8k ? by eq.26,27. c=6.8nf by eq.33. then r=22k ? (eq.34) and r1=1k ? (eq.35). c r l r esr = z z f c 1 r f c 1 r 1 r ? ? ? ? ? ? ? ? ? =
PM6685 other parts design 43/52 9 other parts design vin filter a vin pin low pass filter is suggested to re duce switching noise. t he low pass filter is shown in the next figure: figure 38. vin pin filter typical components values are: r=3.9 ? and c=4.7uf. vcc filter a vcc low pass filter helps to reject switching commutations noise: figure 39. inductor current waveforms typical components values are: r=47 ? and c=1uf. vref capacitor a 10nf to 100nf ceramic capacitor on vref pin must be added to ensure noise rejection. ldo3 and ldo5 output capacitors bypass the output of each linear regulator with 1uf ceramic capacitor closer to the ldo pin and a 4.7uf tantalum capacitor (esr=2 ? ). in most applicative conditions a 4.7uf ceramic output capacitor can be e nough to ensu re stability. v v i i n n 1 1 0 0 0 0 p p f f r r input voltage c c v v c c c c r r c c l l d d o o 5 5
other parts design PM6685 44/52 bootstrap circuit the external bootstrap circuit is represented in the next figure: figure 40. bootstrap circuit the bootstrap circuit capacitor value cboot must provide the total gate charge to the high side mosfet during turn on phase. a typical value is 100nf. the bootstrap diode d must charge the capacit or during the off time phases. the maximum rated voltage must be higher than vinmax. a resistor rboot on the boot pin could be added in order to reduce noise when the phase node rises up, working like a gate resistor for the turn on phase of the high side mosfet. p p h h a a s s e e c c b b o o o o t t r r b b o o o o t t l l d d o o 5 5 b b o o o o t t d d l l
PM6685 design example 45/52 10 design example the following design example considers an input voltage from 7v to 16v. the two switching outputs must deliver a maximum current of 5a. the selected switching frequencies are 200khz for the 5v section and 300khz for the 3.3v section. 10.1 inductor selection out5: i load = 5a, 60% ripple current. equation 34 we choose standard value l = 6 uh ? i l(max) = 2.86a @v in =16v i lrms = 5.07a i peak = 5a + 0.95a = 6.43a out3: iload = 5a, 50% ripple current. equation 35 we choose standard value l=4 uh. ? i l(max) = 2.2a @v in =16v i lrms = 5.04a i peak = 5a + 1.1a = 6.1a 10.2 output capacitor selection we would like to have an output ripple greater than 35mv. out5: poscap 6tpb330m out3: poscap 6tpb330m h 7 . 5 5 6 . 0 v 16 khz 200 ) v 5 v 16 ( v 5 l ? ? ? ? ? = h 52 . 3 5 5 . 0 v 16 khz 300 ) 33 . 3 16 ( 33 . 3 l ? ? ? ? ? =
design example PM6685 46/52 10.3 power mosfets out5: high side: sts12nh3ll low side: sts12nh3ll out3: high side: sts12nh3ll low side: sts12nh3ll 10.4 current limit out5: equation 36 equation 37 (let?s assume the maximum temperature tmax = 75c in r dson calculation) out3: equation 38 equation 39 (let?s assume tmax = 75c in rdson calculation) a 22 . 4 2 (min) i (max) i (min) i l load lvalley = ? ? = ? ? ? 686 m 25 . 16 a 100 a 22 . 4 r csense a 19 . 4 2 (min) i (max) i (min) i l load lvalley = ? ? = ? ? ? 681 m 25 . 16 a 100 a 19 . 4 r csense
PM6685 design example 47/52 10.5 input capacitor maximum input capacitor rms current is about 3.4a. then i cinrms > 3.4a we put three 10uf ceramic capacitors with irms = 1.5a. 10.6 synchronous rectifier out5: schottky diode stps1l30m out3: schottky diode stps1l30m 10.7 integrator loop (refer to figure 30 on page 24 ) out5: the ripple is greater than 30mv, then the virtual esr network is not required. c int =1nf; c filt = 47pf; r int = 1k ? out3: the ripple is greater than 30mv, then the virtual esr network is not required. c int =1nf; c filt = 47pf; r int = 1k ? 10.8 layout guidelines the layout is very important in terms of effi ciency, stability and noise of the system. it is possible to refer to the PM6685 demoboard for a complete layout example. for good pc board layout follows these guidelines: place on the top side all the power componen ts (inductors, input and output capacitors, mosfets and diodes). refer them to a power ground plan, pgnd. if possible, reserve a layer to pgnd plan. the pgnd plan is th e same for both the switching sections. ac current paths layout is very critical (see figure 41 on page 48 ). the first priority is to minimize their length. trace the ls mosfet connection to pgnd plan as short as possible. place the synchronous diode d near the ls mosfet. connect the ls mosfet drain to the switching node with a short trace. place input capacitors near hs mosfet drain. it is recommended to use the same input voltage plan for both the switching sections, in order to put together all input capacitors. place all the sensitive analog signals (feedbacks, voltage reference, current sense paths) on the bottom side of the board or in an inner layer. isolate them from the power top side with a signal ground layer, sgnd. connect the sgnd and pgnd plans only in one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near the pgnd device pin. place the device on the top or on the bottom size and connect the exposed pad and the sgnd pins to the sgnd plan (see figure 41 on page 48 ).
design example PM6685 48/52 figure 41. current paths, ground connection and driver traces layout as general rule, make the high side and low side drivers traces wide and short. the high side driver is powered by the bootstrap circuit. it?s very important to place capacitor cboot and diode dboot as near as possible to the hgate pin (for example on the layer opposite to the device ). route hgate and ph ase traces as near as possible in order to minimize the area between them. the low side gate driver is powered by the 5v linear regulator output. placing pgnd and lgate pins near the low side mosfets reduces the length of the traces and the crosstalk noise between the two sections. the linear regulator outputs are referred to sgnd as long as the reference voltage vref. place their output filtering capacitors as near as possible to the device. place input filtering capacitors near vcc and vin pins. it would be better if the feedback networks connected to comp and out pins are ?referred? to sgnd in the same point as reference voltage vref. to avoid capacitive coupling place these traces as far as po ssible from the gate drivers and phase (switching) paths. place the current sense traces on the bo ttom side. use a dedicated connection between the switching node and the current limit resistor rcsense.
PM6685 package mechanical data 49/52 11 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free se cond level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . table 18. vfqfpn 5x5x1.0 32l pitch 0.50 dim. databook (mm) min typ max a0.80.91 a1 0 0.02 0.05 a3 0.2 b 0.18 0.25 0.3 d4.8555.15 d2 see exposed pad variations (2) e4.8555.15 e2 see exposed pad variations (2) e0.5 l 0.3 0.4 0.5 ddd 0.05 table 19. exposed pad variations (1)(2) d2 1. vfqfpn stands for thermally enhanced very th in fine pitch quad flat package no lead. very thin: a = 1.00mm max. 2. dimensions d2 & e2 are not in accordance with jedec. e2 min typ max min typ max 2.90 3.10 3.20 2.90 3.10 3.20
package mechanical data PM6685 50/52 figure 42. package dimensions
PM6685 revision history 51/52 12 revision history * table 20. document revision history date revision changes 17-jan-2006 1 initial release 21-apr-2006 2 few updates 03-may-2006 3 graphical updates 29-jun-2006 4 mechanical data updated 11-sep-2006 5 changes electrical characteristics, added comp value skip mode, pin out updated 24-oct-2006 6 order code table updated 18-oct-2007 7 updated: current sensing option and absolute maximum ratings table 3 on page 9 .
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